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[2010.6.15.(화)] 물리전자연구실-BK21정보기술사업단 공동워크샵

▶물리전자연구실-BK21정보기술사업단 공동워크샵◀


Joint Seminar on Advanced Semiconductor Device and Process Modeling


Attempts to defeat the perceived limits of scaling conventional bulk Si CMOS devices necessarily center on novel structures and devices of nanometer-scale dimensions. This reduction of the size of electronic devices to 'few electron structures' poses significant challenges when attempting to understand the physics of charge transport.

In this seminar, the theoretical and numerical approaches for nanoscale devices will be presented. This topic includes an accurate understanding of band structure properties, electronic transport and their application on the novel devices. In addition, the Quasi-Ballistic transport model will be discussed based on the Virtual Source model.

The perspectives from Industry will be also presented including two topics: 1) Compact process modeling of amorpization after the ion implantation using Kinetic Monte Carlo Simulation 2) The methodology and the results of simulation on the stress engineering for maintaining performance gain under gate length of 40nm


■ 일 시 : 2010년 6월 15일(화) 14:00-16:40

■ 장 소 : 서울대학교 반도체공동연구소 설계연구관 3층 도연홀

■ 주 최 : 서울대학교 물리전자연구실

              서울대학교 BK21 정보기술사업단

              나노응용시스템연구센터, 반도체공동연구소


■ 문 의 : 최예진 (Tel : 02-880-1797 / e-mail :

■ 첨 부 : 워크샵 안내문(프로그램 및 연사소개) 1부.



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